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A Re-design Technique for Datapath Modules in Error Tolerant Applications.

, и . ATS, стр. 431-437. IEEE Computer Society, (2008)

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Sandeep Gupta

Varun K Gupta

Sandeep Sadanandan

Sandeep Nambiar

Sandeep Kumar

 

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A 1-GS/s 11-bit ADC With 55-dB SNDR, 250-mW Power Realized by a High Bandwidth Scalable Time-Interleaved Architecture., , и . IEEE J. Solid State Circuits, 41 (12): 2650-2657 (2006)Test Generation for Weak Resistive Bridges., , и . ATS, стр. 265-272. IEEE, (2006)Introducing Redundant Computations in a Behavior for Reducing BIST Resources., , и . DAC, стр. 548-553. ACM Press, (1998)Test Generation for Maximizing Ground Bounce for Internal Circuitry with Reconvergent Fan-out., , и . VTS, стр. 358-367. IEEE Computer Society, (2001)Test generation in VLSI circuits for crosstalk noise., , и . ITC, стр. 641-650. IEEE Computer Society, (1998)Analytic Models for Crosstalk Delay and Pulse Analysis Under Non-Ideal Inputs., , и . ITC, стр. 809-818. IEEE Computer Society, (1997)LT-RTPG: a new test-per-scan BIST TPG for low heat dissipation., и . ITC, стр. 85-94. IEEE Computer Society, (1999)Test generation for crosstalk-induced delay in integrated circuits., , и . ITC, стр. 191-200. IEEE Computer Society, (1999)Extending pre-silicon delay models for post-silicon tasks: Validation, diagnosis, delay testing, and speed binning., и . VTS, стр. 1-6. IEEE Computer Society, (2013)Process variation oriented delay testing of SRAMs., и . VTS, стр. 1-6. IEEE Computer Society, (2016)