( en | de | ru )

 

Disambiguation of "Butzen, Paulo F."

Author of the publication

copydeleteadd this publication to your clipboard
The Impact of Logic Gates Susceptibility in Overall Circuit Reliability Analysis.

, , , , and . ISCAS, page 1610-1614. IEEE, (2022)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Andrea Butzen

Milan Paulovic

Reiner Butzen

Reiner Butzen

Reiner Butzen

 

Other publications of authors with the same name

Optimizing machine learning logic circuits with constant signal propagation., , , and . Integr., (2022)BTI, HCI and TDDB aging impact in flip-flops., , , and . Microelectron. Reliab., 53 (9-11): 1355-1359 (2013)Evaluation of Digital Circuit Design by Combining Two - and Multi-Level Approximate Logic Synthesis., , , and . ISVLSI, page 1-6. IEEE, (2023)Soft Error Sensibility Window at FinFET DICE SRAM., , , and . LASCAS, page 1-4. IEEE, (2021)A Novel SPICE Model of Memristive Devices with Threshold Current Based Control., and . SBCCI, page 1-6. IEEE, (2018)Reliability analysis of majority voters under permanent faults., , and . LATS, page 180. IEEE, (2016)Exploring BDDs to reduce test pattern set., , and . LATS, page 1-4. IEEE, (2017)Simple and accurate method for fast static currentestimation in cmos complex gates with interaction ofleakage mechanisms., , , , , and . ACM Great Lakes Symposium on VLSI, page 407-410. ACM, (2008)A Two-Level Approximate Logic Synthesis Combining Cube Insertion and Removal., , , , and . CoRR, (2021)Leakage Analysis Considering the Effect of Inter-Cell Wire Resistance for Nanoscaled CMOS Circuits., , , and . J. Low Power Electron., 6 (1): 192-200 (2010)