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Disambiguation of "Mandal, Debashis"

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Implementation of CMOS Low-power Integer-N Frequency Synthesizer for SOC Design.

, and . J. Comput., 3 (4): 31-38 (2008)

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Debashis Chakraborty

Avradip Mandal

Soumyajit Mandal

Dipankar Mandal

Oliver Mandal

 

Other publications of authors with the same name

Low-Power/Low-Voltage Integrated CMOS Sense Resistor-Free Analog Power/Current Sensor Compatible With High-Voltage Switching DC-DC Converter., , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 66-I (6): 2208-2218 (2019)A 91%-Efficiency Envelope-Tracking Modulator Using Hysteresis-Controlled Three-Level Switching Regulator and Slew-Rate-Enhanced Linear Amplifier for LTE-80MHz Applications., , , and . ISSCC, page 428-430. IEEE, (2019)High voltage tolerant output buffer design for mixed voltage interfaces., and . ISCAS (5), page 4277-4280. IEEE, (2005)A 100-mA, 99.11% Current Efficiency, 2-mVpp Ripple Digitally Controlled LDO With Active Ripple Suppression., , , and . IEEE Trans. Very Large Scale Integr. Syst., 25 (2): 696-704 (2017)A Disturbance-Free Built-In Self-Test and Diagnosis Technique for DC-DC Converters., , , , , , and . ACM Trans. Design Autom. Electr. Syst., 23 (2): 25:1-25:22 (2018)Online Built-In Self-Test of High Switching Frequency DC-DC Converters Using Model Reference Based System Identification Techniques., , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 65-I (2): 818-831 (2018)Adaptively Biased Output Cap-Less NMOS LDO With 19 ns Settling Time., , , and . IEEE Trans. Circuits Syst. II Express Briefs, 66-II (2): 167-171 (2019)Towards an Ontology for Enterprise Level Information Security Policy Analysis., and . ICISSP, page 492-499. SCITEPRESS, (2021)Disturbance-free BIST for loop characterization of DC-DC buck converters., , , , , , , and . VTS, page 1-6. IEEE Computer Society, (2015)Spur reducing architecture of frequency synthesiser using switched capacitors., , and . IET Circuits Devices Syst., 8 (4): 237-245 (2014)