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A New Simultaneous Circuit Partitioning and Chip Placement Approach Based on Simulated Annealing., и . DAC, стр. 36-39. IEEE Computer Society Press, (1990)Containing the Nanometer "Pandora-Box": Cross-Layer Design Techniques for Variation Aware Low Power Systems., , и . IEEE J. Emerg. Sel. Topics Circuits Syst., 1 (1): 19-29 (2011)Timing Noise Characterization of High-Speed Digital Bit Sequences Using Incoherent Subsampling and Algorithmic Clock Recovery., , и . IEEE Trans. Instrumentation and Measurement, 63 (12): 2733-2749 (2014)Concurrent Error Detection in Nonlinear Digital Circuits Using Time-Freeze Linearization., и . IEEE Trans. Computers, 46 (11): 1208-1218 (1997)Real-time use-aware adaptive MIMO RF receiver systems for energy efficiency under BER constraints., , , и . DAC, стр. 56:1-56:7. ACM, (2013)Partial Reset Methodology and Experiments for Improving Random-Pattern Testability and BIST of Sequential Circuits., , и . J. Electron. Test., 14 (3): 259-272 (1999)Performance-Optimized Design for Parametric Reliability., , , , и . J. Electron. Test., 24 (1-3): 129-141 (2008)Dynamic Test Stimulus Adaptation for Analog/RF Circuits Using Booleanized Models Extracted From Hardware., , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 39 (10): 2006-2019 (2020)On the C-Testability of Generalized Counters., и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 6 (5): 713-726 (1987)Application of the Reactivity Index to Propose Intra and Intermolecular Reactivity in Catalytic Materials.. International Conference on Computational Science (3), том 3993 из Lecture Notes in Computer Science, стр. 77-81. Springer, (2006)