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A 9-M tr. access network system-on-a-chip for mega-bit Internet access at home., , , , , , , , , and 2 other author(s). CICC, page 231-234. IEEE, (2000)A 2.1-to-2.8-GHz Low-Phase-Noise All-Digital Frequency Synthesizer With a Time-Windowed Time-to-Digital Converter., , , , and . IEEE J. Solid State Circuits, 45 (12): 2582-2590 (2010)A 7-nm FinFET 1.2-TB/s/mm2 3D-Stacked SRAM Module With 0.7-pJ/b Inductive Coupling Interface Using Over-SRAM Coil and Manchester-Encoded Synchronous Transceiver., , , , and . IEEE J. Solid State Circuits, 58 (7): 2075-2086 (2023)A 7-nm FinFET 1.2-TB/s/mm2 3D-Stacked SRAM with an Inductive Coupling Interface Using Over-SRAM Coils and Manchester-Encoded Synchronous Transceivers., , , , and . HCS, page 1-14. IEEE, (2022)Energy-efficient AES SubBytes transformation circuit using asynchronous circuits for ultra-low voltage operation., , , , and . IEICE Electron. Express, 12 (4): 20141157 (2015)An Energy-Efficient 24T Flip-Flop Consisting of Standard CMOS Gates for Ultra-Low Power Digital VLSIs., , , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 98-A (12): 2600-2606 (2015)Live Demonstration: A Non-Contact Transmission Line Connector for USB3.1 HD-Video Streaming., , , , and . ISCAS, page 1. IEEE, (2019)A 24-transistor static flip-flop consisting of nors and inverters for low-power digital vlsis., , , , and . NEWCAS, page 137-140. IEEE, (2014)A 2.1-to-2.8GHz all-digital frequency synthesizer with a time-windowed TDC., , , , and . ISSCC, page 470-471. IEEE, (2010)Polyomino: A 3D-SRAM-Centric Accelerator for Randomly Pruned Matrix Multiplication With Simple Reordering Algorithm and Efficient Compression Format in 180-nm CMOS., , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 70 (9): 3440-3450 (September 2023)