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Efficient FPGA-based QPSK Demodulation Loops: Application to the DVB Standard., , , and . FPL, volume 2438 of Lecture Notes in Computer Science, page 102-111. Springer, (2002)Area-Efficient 2-D Shift-Variant Convolvers for FPGA-based Digital Image Processing., , , , and . FPL, page 578-581. IEEE, (2005)Area-efficient 2-D shift-variant convolvers for FPGA-based digital image processing., and . IEEE Trans. Circuits Syst. II Express Briefs, 53-II (2): 105-109 (2006)Configurable Hardware/Software Architecture for Data Acquisition: Implementation on FPGA., , , , , and . FPL, page 241-246. IEEE, (2005)Area-optimized implementation of quadrature direct digital frequency synthesizers on LUT-based FPGAs., and . IEEE Trans. Circuits Syst. II Express Briefs, 50 (3): 135-138 (2003)Flexible hardware-friendly digital architecture for 2-D separable convolution-based scaling., and . IEEE Trans. Circuits Syst. II Express Briefs, 53-II (7): 522-526 (2006)Power analysis and estimation tool integrated with XPOWER., , , and . FPGA, page 259. ACM, (2004)Optimized FPGA-implementation of quadrature DDS., and . ISCAS (5), page 369-372. IEEE, (2002)Quadrature direct digital frequency synthesizers: area-optimized design map for LUT-based FPGAs., and . ISCAS (2), page 260-263. IEEE, (2003)Implementing High-Speed Double-Data Rate (DDR) SDRAM Controllers on FPGA., , , and . FPL, volume 3203 of Lecture Notes in Computer Science, page 279-288. Springer, (2004)