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Disambiguation of "Ooi, Chia Yee"

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An integrated DFT solution for power reduction in scan test applications by low power gating scan cell.

, , , , and . Integr., (2017)

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Chia Ching Ooi

Charles Woei-Jye Yee

Hernani Tiago Yee Madeira

Sun Yee

Nicole Yee

 

Other publications of authors with the same name

An integrated DFT solution for power reduction in scan test applications by low power gating scan cell., , , , and . Integr., (2017)Packet logging mechanism for adaptive online fault detection on Network-on-Chip., , , , and . ISCAS, page 1760-1763. IEEE, (2014)A Network-on-Chip simulation framework for homogeneous Multi-Processor System-on-Chip., , , and . ASICON, page 175-179. IEEE, (2011)Ping-lock round robin arbiter., , , and . Microelectron. J., (2017)A New Class of Sequential Circuits with Acyclic Test Generation Complexity., and . ICCD, page 425-431. IEEE, (2006)rrBox: A Remote Dynamically Reconfigurable Middlebox for Network Protection., , and . CANDAR, page 219-225. IEEE Computer Society, (2014)Analysis of Test Generation Complexity for Stuck-At and Path Delay Faults Based on tauk-Notation., , and . IEICE Trans. Inf. Syst., 90-D (8): 1202-1212 (2007)A Nonscan Design-for-Testability Method for Register-Transfer-Level Circuits to Guarantee Linear-Depth Time Expansion Models., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 27 (9): 1535-1544 (2008)A New Design-for-Testability Method Based on Thru-Testability., and . J. Electron. Test., 27 (5): 583-598 (2011)Low Latency Network-on-Chip Router Microarchitecture Using Request Masking Technique., , and . Int. J. Reconfigurable Comput., (2015)