Author of the publication

In-Situ Delay Characterization and Local Supply Voltage Adjustment for Compensation of Local Parametric Variations.

, , , , and . IEEE J. Solid State Circuits, 42 (7): 1583-1592 (2007)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

Low power design of the X-GOLD® SDR 20 baseband processor., , , , , , , and . DATE, page 792-793. IEEE Computer Society, (2010)A 90nm CMOS low-power GSM/EDGE multimedia-enhanced baseband processor with 380MHz ARM9 and mixed-signal extensions., , , , , , , , , and 9 other author(s). ISSCC, page 952-961. IEEE, (2006)Design Aspects and Technological Scaling Limits of ZigZag Circuit Block Switch-Off Schemes., , , , and . VLSI-SOC, page 246-251. Technische Universität Darmstadt, Insitute of Microelectronic Systems, (2003)Impact of Gate Leakage on Efficiency of Circuit Block Switch-Off Schemes., , , , , and . VLSI-SoC (Selected Papers), volume 200 of IFIP, page 229-245. Springer, (2003)Two Level Compact Simulation Methodology for Timing Analysis of Power-Switched Circuits., , , and . PATMOS, volume 3254 of Lecture Notes in Computer Science, page 789-798. Springer, (2004)Dynamic state-retention flip-flop for fine-grained power gating with small design and power overhead., , , , , , and . IEEE J. Solid State Circuits, 41 (7): 1654-1661 (2006)An ultra low-power adiabatic adder embedded in a standard 0.13μm CMOS environment., , , , , , and . ESSCIRC, page 599-602. IEEE, (2003)The impact of intra-die device parameter variations on path delays and on the design for yield of low voltage digital circuits., , , and . ISLPED, page 237-242. IEEE, (1996)The impact of intra-die device parameter variations on path delays and on the design for yield of low voltage digital circuits., , , and . IEEE Trans. Very Large Scale Integr. Syst., 5 (4): 360-368 (1997)Architecture and implementation of a Software-Defined Radio baseband processor., , , , , , , , , and 8 other author(s). ISCAS, page 2193-2196. IEEE, (2011)