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Edge Synthesis Block: A Building Unit for Real-Time Single Image Super Resolution.

, , , , and . ICIP, page 915-919. IEEE, (2023)

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Edge Synthesis Block: A Building Unit for Real-Time Single Image Super Resolution., , , , and . ICIP, page 915-919. IEEE, (2023)A novel method to regenerate an optimal CNN by exploiting redundancy patterns in the network., , , and . ICIP, page 4407-4411. IEEE, (2017)An Intelligent Bandwidth Manager for CNN Applications on Embedded Devices., , , , , , , and . ICIP, page 4173-4177. IEEE, (2018)Accurate and Efficient Fixed Point Inference for Deep Neural Networks., , , , , and . ICIP, page 1847-1851. IEEE, (2018)Intra mode power saving methodology for CGRA-based reconfigurable processor architectures., , , , , and . ISCAS, page 714-717. IEEE, (2016)Efficient deblocking filter implementation on reconfigurable processor., , , and . ICASSP, page 1050-1054. IEEE, (2016)Fast cycle-accurate compile based simulator for reconfigurable processor., , , and . ISCAS, page 1-4. IEEE, (2017)Low Complex & High Accuracy Computation Approximations to Enable On-Device RNN Applications., , , , , , and . ISCAS, page 1-5. IEEE, (2019)Optimal SDRAM Buffer Allocator for Efficient Reuse of Layer IO in CNNs Inference Framework., , , , , and . ISCAS, page 1-5. IEEE, (2018)