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The split register file.

, , , и . DATE, стр. 945-948. IEEE Computer Society, (2010)

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Rafael Eurico Block Siqueira Cavalcanti Veras

Leonardo Verano Gamboa

Galo Vera Chamaza

Antonio Vera

Peter Veranneman-Watervliet

 

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A Fast and Accurate Approach to Analyze Cache Memory Behavior (Research Note)., , , и . Euro-Par, том 1900 из Lecture Notes in Computer Science, стр. 194-198. Springer, (2000)TRAMS Project: Variability and Reliability of SRAM Memories in sub-22 nm Bulk-CMOS Technologies., , , , , , , и . FET, том 7 из Procedia Computer Science, стр. 148-149. Elsevier, (2011)On-line Failure Detection in Memory Order Buffers., , , и . ITC, стр. 1-10. IEEE Computer Society, (2008)Low Vccmin fault-tolerant cache with highly predictable performance., , , , и . MICRO, стр. 111-121. ACM, (2009)VCTA: A Via-Configurable Transistor Array regular fabric., , , , , и . VLSI-SoC, стр. 335-340. IEEE, (2010)Online error detection and correction of erratic bits in register files., , , , и . IOLTS, стр. 81-86. IEEE Computer Society, (2009)On-Line Failure Detection and Confinement in Caches., , , , и . IOLTS, стр. 3-9. IEEE Computer Society, (2008)Control-Flow Recovery Validation Using Microarchitectural Invariants., , , и . DFT, стр. 209-216. IEEE Computer Society, (2011)Framework for economical error recovery in embedded cores., , и . IOLTS, стр. 146-153. IEEE, (2014)Penelope: The NBTI-Aware Processor., , и . MICRO, стр. 85-96. IEEE Computer Society, (2007)