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21.1 A Fully Integrated Genetic Variant Discovery SoC for Next-Generation Sequencing.

Y. Wu, Y. Chen, C. Yang, C. Lee, C. Yu, N. Chang, L. Chen, J. Chang, C. Lin, H. Chen, C. Chen, J. Hung, and C. Yang. ISSCC, page 322-324. IEEE, (2020)

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Tze-Lung Chen

Yen-Chih Chen

Yen-Ta Chen

Shing-lung Chen

Chen-Shyong Yen

Other publications of authors with the same name

A fast heuristic approach for parametric yield enhancement of analog designs.C. Liu, Y. Chen, C. Kuo, and I. Tsai. ACM Trans. Design Autom. Electr. Syst., 17 (3): 35:1-35:20 (2012)Stochastic Data-driven Hardware Resilience to Efficiently Train Inference Models for Stochastic Hardware Implementations.B. Zhang, L. Chen, and N. Verma. ICASSP, page 1388-1392. IEEE, (2019)Simultaneous optimization for low dropout regulator and its error amplifier with process variation.Y. Chen, G. Chu, Y. Lien, C. Lee, and C. Liu. VLSI-DAT, page 1-4. IEEE, (2014)Neural Network Training With Stochastic Hardware Models and Software Abstractions.B. Zhang, L. Chen, and N. Verma. IEEE Trans. Circuits Syst. I Regul. Pap., 68 (4): 1532-1542 (2021)A Fully Integrated End-to-End Genome Analysis Accelerator for Next-Generation Sequencing.Y. Chen, C. Yang, Y. Wu, C. Lee, W. Chen, L. Lin, N. Chang, C. Lin, C. Chen, J. Hung and 1 other author(s). ISSCC, page 44-45. IEEE, (2023)A 3-D IC for Mitigating Energy of Memory Accessing and Data Movement in Accelerator- Based Streaming Architectures.L. Chen, S. Tao, and N. Verma. IEEE J. Solid State Circuits, 54 (6): 1778-1788 (2019)REscope: High-dimensional Statistical Circuit Simulation towards Full Failure Region Coverage.W. Wu, W. Xu, R. Krishnan, Y. Chen, and L. He. DAC, page 82:1-82:6. ACM, (2014)21.1 A Fully Integrated Genetic Variant Discovery SoC for Next-Generation Sequencing.Y. Wu, Y. Chen, C. Yang, C. Lee, C. Yu, N. Chang, L. Chen, J. Chang, C. Lin, H. Chen and 3 other author(s). ISSCC, page 322-324. IEEE, (2020)A High-Throughput FPGA Accelerator for Short-Read Mapping of the Whole Human Genome.Y. Chen, B. Chang, C. Yang, and T. Chiueh. IEEE Trans. Parallel Distributed Syst., 32 (6): 1465-1478 (2021)An FM-Index Based High-Throughput Memory-Efficient FPGA Accelerator for Paired-End Short-Read Mapping.C. Yang, Y. Wu, Y. Chen, C. Lee, J. Hung, and C. Yang. IEEE Trans. Biomed. Circuits Syst., 17 (6): 1331-1341 (December 2023)

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Disambiguation of "Chen, Yen-Lung"

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21.1 A Fully Integrated Genetic Variant Discovery SoC for Next-Generation Sequencing.

Please choose a person to relate this publication to

Tze-Lung Chen

Yen-Chih Chen

Yen-Ta Chen

Shing-lung Chen

Chen-Shyong Yen

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Chen, Yen-Lung"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML 21.1 A Fully Integrated Genetic Variant Discovery SoC for Next-Generation Sequencing.

Please choose a person to relate this publication to

Tze-Lung Chen

Yen-Chih Chen

Yen-Ta Chen

Shing-lung Chen

Chen-Shyong Yen

Other publications of authors with the same name

Disambiguation

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history of this post
URL
DOI
BibTeX
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Chicago
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21.1 A Fully Integrated Genetic Variant Discovery SoC for Next-Generation Sequencing.