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Disambiguation of "Chen, Lung-Yen"

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A 3-D IC for Mitigating Energy of Memory Accessing and Data Movement in Accelerator- Based Streaming Architectures.

, , and . IEEE J. Solid State Circuits, 54 (6): 1778-1788 (2019)

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Tze-Lung Chen

Yen-Chih Chen

Yen-Ta Chen

Shing-lung Chen

Chen-Shyong Yen

 

Other publications of authors with the same name

Stochastic Data-driven Hardware Resilience to Efficiently Train Inference Models for Stochastic Hardware Implementations., , and . ICASSP, page 1388-1392. IEEE, (2019)A fast heuristic approach for parametric yield enhancement of analog designs., , , and . ACM Trans. Design Autom. Electr. Syst., 17 (3): 35:1-35:20 (2012)Neural Network Training With Stochastic Hardware Models and Software Abstractions., , and . IEEE Trans. Circuits Syst. I Regul. Pap., 68 (4): 1532-1542 (2021)Simultaneous optimization for low dropout regulator and its error amplifier with process variation., , , , and . VLSI-DAT, page 1-4. IEEE, (2014)A Fully Integrated End-to-End Genome Analysis Accelerator for Next-Generation Sequencing., , , , , , , , , and 1 other author(s). ISSCC, page 44-45. IEEE, (2023)A 3-D IC for Mitigating Energy of Memory Accessing and Data Movement in Accelerator- Based Streaming Architectures., , and . IEEE J. Solid State Circuits, 54 (6): 1778-1788 (2019)REscope: High-dimensional Statistical Circuit Simulation towards Full Failure Region Coverage., , , , and . DAC, page 82:1-82:6. ACM, (2014)21.1 A Fully Integrated Genetic Variant Discovery SoC for Next-Generation Sequencing., , , , , , , , , and 3 other author(s). ISSCC, page 322-324. IEEE, (2020)A 975-mW Fully Integrated Genetic Variant Discovery System-on-Chip in 28 nm for Next-Generation Sequencing., , , , , , , , , and 3 other author(s). IEEE J. Solid State Circuits, 56 (1): 123-135 (2021)Behavior-level yield enhancement approach for large-scaled analog circuits., , , , and . DAC, page 903-908. ACM, (2010)