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Ultra-High-Speed Image Signal Accumulation Sensor., , , , , , и . Sensors, 10 (4): 4100-4113 (2010)CLAHE implementation on a low-end FPGA board by high-level synthesis., , , и . CANDAR (Workshops), стр. 282-285. IEEE, (2020)A High Speed License Plate Recognition System on an FPGA., , , , , и . FPL, стр. 554-557. IEEE, (2007)CLAHE Implementation and Evaluation on a Low-End FPGA Board by High-Level Synthesis., , , и . IEICE Trans. Inf. Syst., 104-D (12): 2048-2056 (2021)Implementation and Evaluation of a High Speed License Plate Recognition System on an FPGA., , , , , и . CIT, стр. 567-572. IEEE Computer Society, (2007)Weighted Least Square Filter for Improving the Quality of Depth Map on FPGA., , , , и . Int. J. Netw. Comput., 12 (2): 425-445 (2022)RT-libSGM: FPGA-Oriented Real-Time Stereo Matching System with High Scalability., , , и . IEICE Trans. Inf. Syst., 106 (3): 337-348 (марта 2023)A neural inverse function for automatic test pattern generation using strictly digital neural networks., , и . VTS, стр. 238-243. IEEE Computer Society, (1993)Weight Least Square Filter for Improving the Quality of Depth Map on FPGA., , , , и . CANDAR (Workshops), стр. 297-300. IEEE, (2021)RT-libSGM: An Implementation of a Real-time Stereo Matching System on FPGA., , , и . HEART, стр. 1-9. ACM, (2022)