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A 6-to-600MS/s Fully Dynamic Ringamp Pipelined ADC with Asynchronous Event-Driven Clocking in 16nm.

, , , , , , and . ISSCC, page 68-70. IEEE, (2019)

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Automated synthesis of complex analog circuits., , , and . ECCTD, page 20-23. IEEE, (2007)A 12-bit 1GS/s ADC With Background Distortion and Split-ADC-Like Gain Calibration., , , , , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 70 (12): 4679-4691 (December 2023)A 4-GS/s 10-ENOB 75-mW Ringamp ADC in 16-nm CMOS With Background Monitoring of Distortion., , , , , , and . IEEE J. Solid State Circuits, 56 (8): 2360-2374 (2021)22.5 A 42GS/s 7b 16nm Massively Time-Interleaved Slope-ADC., , , , , , , and . ISSCC, page 396-398. IEEE, (2024)A 47.5MHz BW 4.7mW 67dB SNDR Ringamp Based Discrete-Time Delta Sigma ADC., , , , , and . ESSCIRC, page 207-210. IEEE, (2021)A 950 MHz Clock 47.5 MHz BW 4.7 mW 67 dB SNDR Discrete Time Delta Sigma ADC Leveraging Ring Amplification and Split-Source Comparator Based Quantizer in 28 nm CMOS., , , , , and . IEEE J. Solid State Circuits, 57 (7): 2068-2077 (2022)A 1-MS/s to 1-GS/s Ringamp-Based Pipelined ADC With Fully Dynamic Reference Regulation and Stochastic Scope-on-Chip Background Monitoring in 16 nm., , , , , and . IEEE J. Solid State Circuits, 56 (4): 1227-1240 (2021)RF-to-Baseband Digitization in 40 nm CMOS With RF Bandpass ΔΣ Modulator and Polyphase Decimation Filter., , , , , , , and . IEEE J. Solid State Circuits, 47 (4): 990-1002 (2012)Calibration Techniques for Optimizing Performance of High-Speed ADCs., , , and . CICC, page 1-8. IEEE, (2023)A 5.5-GHz Background-Calibrated Subsampling Polar Transmitter With -41.3-dB EVM at 1024 QAM in 28-nm CMOS., , , , , and . IEEE J. Solid State Circuits, 54 (4): 1059-1073 (2019)