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A 6-to-600MS/s Fully Dynamic Ringamp Pipelined ADC with Asynchronous Event-Driven Clocking in 16nm.

B. Hershberg, B. van Liempd, N. Markulic, J. Lagos, E. Martens, D. Dermit, and J. Craninckx. ISSCC, page 68-70. IEEE, (2019)

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Nereo Kalebi

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A 9.2-12.7 GHz Wideband Fractional-N Subsampling PLL in 28 nm CMOS With 280 fs RMS Jitter.K. Raczkowski, N. Markulic, B. Hershberg, and J. Craninckx. IEEE J. Solid State Circuits, 50 (5): 1203-1213 (2015)A Self-Calibrated 16-GHz Subsampling-PLL-Based Fast-Chirp FMCW Modulator With 1.5-GHz Bandwidth.Q. Shi, K. Bunsen, N. Markulic, and J. Craninckx. IEEE J. Solid State Circuits, 54 (12): 3503-3512 (2019)A 3.2GS/s 10 ENOB 61mW Ringamp ADC in 16nm with Background Monitoring of Distortion.B. Hershberg, D. Dermit, B. van Liempd, E. Martens, N. Markulic, J. Lagos, and J. Craninckx. ISSCC, page 58-60. IEEE, (2019)A 1-MS/s to 1-GS/s Ringamp-Based Pipelined ADC With Fully Dynamic Reference Regulation and Stochastic Scope-on-Chip Background Monitoring in 16 nm.B. Hershberg, N. Markulic, J. Lagos, E. Martens, D. Dermit, and J. Craninckx. IEEE J. Solid State Circuits, 56 (4): 1227-1240 (2021)A Fractional-n subsampling PLL based on a digital-to-time converter.N. Markulic, K. Raczkowski, P. Wambacq, and J. Craninckx. MIPRO, page 66-71. IEEE, (2016)Calibration Techniques for Optimizing Performance of High-Speed ADCs.E. Martens, N. Markulic, J. Lagos-Benites, and J. Craninckx. CICC, page 1-8. IEEE, (2023)A Self-Calibrated 16GHz Subsampling-PLL-Based 30s Fast Chirp FMCW Modulator with 1.5GHz Bandwidth and 100kHz rms Error.Q. Shi, K. Bunsen, N. Markulic, and J. Craninckx. ISSCC, page 408-410. IEEE, (2019)Asynchronous Event-Driven Clocking and Control in Pipelined ADCs.B. Hershberg, B. van Liempd, N. Markulic, J. Lagos, E. Martens, D. Dermit, and J. Craninckx. IEEE Trans. Circuits Syst. I Regul. Pap., 68 (7): 2813-2826 (2021)24.7 A 673µW 1.8-to-2.5GHz dividerless fractional-N digital PLL with an inherent frequency-capture capability and a phase-dithering spur mitigation for IoT applications.Y. He, Y. Liu, T. Kuramochi, J. van den Heuvel, B. Busze, N. Markulic, C. Bachmann, and K. Philips. ISSCC, page 420-421. IEEE, (2017)A 1MS/s to 1GS/s Ringamp-Based Pipelined ADC with Fully Dynamic Reference Regulation and Stochastic Scope-on-Chip Background Monitoring in 16nm.B. Hershberg, N. Markulic, J. Lagos, E. Martens, D. Dermit, and J. Craninckx. VLSI Circuits, page 1-2. IEEE, (2020)

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A 6-to-600MS/s Fully Dynamic Ringamp Pipelined ADC with Asynchronous Event-Driven Clocking in 16nm.

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Nereo Kalebi

Other publications of authors with the same name

Disambiguation

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Disambiguation of "Markulic, Nereo"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A 6-to-600MS/s Fully Dynamic Ringamp Pipelined ADC with Asynchronous Event-Driven Clocking in 16nm.

Please choose a person to relate this publication to

Nereo Kalebi

Other publications of authors with the same name

Disambiguation

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URL
DOI
BibTeX
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APA
Chicago
DIN 1505
Harvard
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A 6-to-600MS/s Fully Dynamic Ringamp Pipelined ADC with Asynchronous Event-Driven Clocking in 16nm.