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Disambiguation of "Chappert, Claude"

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Synthesis of Finite State Machines with Magnetic Domain Wall Logic.

, , , , , , and . ISCAS, page 133-136. IEEE, (2007)

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Claude Velo

Claude Brodski

Claude Haan

Claude Muller

Claude Imobersteg

 

Other publications of authors with the same name

Design of embedded MRAM macros for memory-in-logic applications., , , , and . ACM Great Lakes Symposium on VLSI, page 155-158. ACM, (2010)Nanodevice-based novel computing paradigms and the neuromorphic approach., , , , and . ISCAS, page 2509-2512. IEEE, (2012)Ultra Low Power Magnetic Flip-Flop Based on Checkpointing/Power Gating and Self-Enable Mechanisms., , , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 61-I (6): 1755-1765 (2014)High Performance SoC Design Using Magnetic Logic and Memory., , , , , , , , , and 2 other author(s). VLSI-SoC (Selected Papers), volume 379 of IFIP Advances in Information and Communication Technology, page 10-33. Springer, (2011)Low power magnetic flip-flop based on checkpointing and self-enable mechanism., , , , and . NEWCAS, page 1-4. IEEE, (2013)Emerging hybrid logic circuits based on non-volatile magnetic memories., , , , , and . NEWCAS, page 1-4. IEEE, (2013)Design and analysis of crossbar architecture based on complementary resistive switching non-volatile memory cells., , , , , , , , , and 4 other author(s). J. Parallel Distributed Comput., 74 (6): 2484-2496 (2014)Spintronics for low-power computing., , , , , , , and . DATE, page 1-6. European Design and Automation Association, (2014)Synthesis of Finite State Machines with Magnetic Domain Wall Logic., , , , , , and . ISCAS, page 133-136. IEEE, (2007)Magnetic Adder Based on Racetrack Memory., , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 60-I (6): 1469-1477 (2013)