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Disambiguation of "Merten, Marcel"

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Design Enablement Flow for Circuits with Inherent Obfuscation based on Reconfigurable Transistors.

, , , , , , , , , , , , , , , and . DATE, page 1-6. IEEE, (2023)

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Merten Niebelschütz

Multifunktionale Nanoanalytik für eine Nanopositionier- und Messmaschine. TU Ilmenau, (2009)

Hans Merten

Anita Merten

Sophie Merten

Alfons Merten

 

Other publications of authors with the same name

A Codeword-based Compactor for On-Chip Generated Debug Data Using Two-Stage Artificial Neural Networks., , and . DFT, page 1-6. IEEE, (2021)Design Enablement Flow for Circuits with Inherent Obfuscation based on Reconfigurable Transistors., , , , , , , , , and 6 other author(s). DATE, page 1-6. IEEE, (2023)Efficient machine learning through evolving combined deep neural networks., , , , and . GECCO Companion, page 215-216. ACM, (2020)Quality Assessment of Logic Locking Mechanisms using Pseudo-Boolean Optimization Techniques., , and . DDECS, page 105-110. IEEE, (2023)ALF: a fitness-based artificial life form for evolving large-scale neural networks., , , and . GECCO Companion, page 225-226. ACM, (2021)Scalable Neuroevolution of Ensemble Learners., , and . GECCO Companion, page 667-670. ACM, (2023)Increasing SAT-Resilience of Logic Locking Mechanisms using Formal Methods., , and . ETS, page 1-6. IEEE, (2023)A Hardware-based Evolutionary Algorithm with Multi-Objective Optimization Operators for On-Chip Transient Fault Detection., , and . VTS, page 1-7. IEEE, (2022)Quality Assessment of RFET-based Logic Locking Protection Mechanisms using Formal Methods., , and . ETS, page 1-2. IEEE, (2022)