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Quality Assessment of RFET-based Logic Locking Protection Mechanisms using Formal Methods.

, , and . ETS, page 1-2. IEEE, (2022)

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Determining Application-Specific Knowledge for Improving Robustness of Sequential Circuits., , , and . IEEE Trans. Very Large Scale Integr. Syst., 27 (4): 875-887 (2019)Ein KI-Verfahren für das Kartenspiel Magic: The Gathering., , , , , and . Inform. Spektrum, 31 (3): 241-248 (2008)Ein KI-Verfahren für das Kartenspiel Magic: The Gathering., , , , , and . Informatiktage, volume S-5 of LNI, page 25-28. GI, (2007)Building Fast Multi Agent Systems Using Hardware Design Languages for High-Throughput Systems., , , and . LDIC, page 400-405. Springer, (2018)Design Enablement Flow for Circuits with Inherent Obfuscation based on Reconfigurable Transistors., , , , , , , , , and 6 other author(s). DATE, page 1-6. IEEE, (2023)Hybrid Architecture for Embedded Test Compression to Process Rejected Test Patterns., , and . ETS, page 1-2. IEEE, (2019)Next generation design for testability, debug and reliability using formal techniques.. University of Bremen, Germany, (2020)RC-IJTAG: A Methodology for Designing Remotely-Controlled IEEE 1687 Scan Networks., , and . DFT, page 1-6. IEEE, (2023)A Hardware-based Evolutionary Algorithm with Multi-Objective Optimization Operators for On-Chip Transient Fault Detection., , and . VTS, page 1-7. IEEE, (2022)Increasing SAT-Resilience of Logic Locking Mechanisms using Formal Methods., , and . ETS, page 1-6. IEEE, (2023)