Author of the publication

Improving Critical Path Identification in Functional Timing Analysis.

, , , and . SBCCI, page 297-302. IEEE Computer Society, (2003)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

3D-Via Driven Partitioning for 3D VLSI Integrated Circuits., , , and . CLEI Electron. J., (2010)Revisiting automated physical synthesis of high-performance clock networks., , and . ACM Trans. Design Autom. Electr. Syst., 18 (2): 31:1-31:27 (2013)Non-uniform clock mesh optimization with linear programming buffer insertion., , and . DAC, page 74-79. ACM, (2010)A study on layout quality of automatic generated cells., , , , and . ICECS, page 651-654. IEEE, (2010)Computational Delay Models to Estimate the Delay of Floating Cubes in CMOS Circuits., , , , , , and . PATMOS, volume 2799 of Lecture Notes in Computer Science, page 501-510. Springer, (2003)Improving Critical Path Identification in Functional Timing Analysis., , , and . SBCCI, page 297-302. IEEE Computer Society, (2003)A cells and I/O pins partitioning refinement algorithm for 3D VLSI circuits., , , and . ICECS, page 852-855. IEEE, (2009)Finding the Critical Delay of Combinational Blocks by Floating Vector Simulation and Path Tracing., , , , and . SBCCI, page 277-282. IEEE Computer Society, (2002)Gate Sizing Minimizing Delay and Area., , , and . ISVLSI, page 315-316. IEEE Computer Society, (2011)A novel scheme to reduce short-circuit power in mesh-based clock architectures., , , and . SBCCI, page 117-122. ACM, (2008)