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Floating-point division algorithms for an x86 microprocessor with a rectangular multiplier.

, , and . ICCD, page 304-310. IEEE, (2007)

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FPGA Resource Reduction Through Truncated Multiplication., , and . FPL, volume 2147 of Lecture Notes in Computer Science, page 574-583. Springer, (2001)Energy-efficient floating-point arithmetic for digital signal processors., , and . ACSCC, page 1823-1827. IEEE, (2011)A Low-Power Multithreaded Processor for Software Defined Radio., , , , , and . VLSI Signal Processing, 43 (2-3): 143-159 (2006)High-Speed Multioperand Decimal Adders., and . IEEE Trans. Computers, 54 (8): 953-963 (2005)Low-Power Multiple-Precision Iterative Floating-Point Multiplier with SIMD Support., , and . IEEE Trans. Computers, 58 (2): 175-187 (2009)Achieving Exascale Capabilities through Heterogeneous Computing., , , , , , , , , and . IEEE Micro, 35 (4): 26-36 (2015)CORDIC-based LMMSE equalizer for Software Defined Radio., , , , , , and . ICSAMOS, page 301-308. IEEE, (2010)Parallel saturating multioperand adders., , , and . CASES, page 172-179. ACM, (2000)Hardware interval multipliers.. RITA, 3 (2): 73-90 (1996)A Decimal Floating-Point Divider Using Newton-Raphson Iteration., and . VLSI Signal Processing, 49 (1): 3-18 (2007)