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Energy-efficient floating-point arithmetic for digital signal processors., , and . ACSCC, page 1823-1827. IEEE, (2011)FPGA Resource Reduction Through Truncated Multiplication., , and . FPL, volume 2147 of Lecture Notes in Computer Science, page 574-583. Springer, (2001)Hardware interval multipliers.. RITA, 3 (2): 73-90 (1996)Low-Power Multiple-Precision Iterative Floating-Point Multiplier with SIMD Support., , and . IEEE Trans. Computers, 58 (2): 175-187 (2009)High-Speed Multioperand Decimal Adders., and . IEEE Trans. Computers, 54 (8): 953-963 (2005)Achieving Exascale Capabilities through Heterogeneous Computing., , , , , , , , , and . IEEE Micro, 35 (4): 26-36 (2015)A Low-Power Multithreaded Processor for Software Defined Radio., , , , , and . VLSI Signal Processing, 43 (2-3): 143-159 (2006)Optimal initial approximations for the Newton-Raphson division algorithm., , and . Computing, 53 (3-4): 233-242 (1994)Low-Cost Per-Core Voltage Domain Support for Power-Constrained High-Performance Processors., , , , and . IEEE Trans. Very Large Scale Integr. Syst., 22 (4): 747-758 (2014)The Sandbridge SB3011 Platform., , , , , , and . EURASIP J. Embed. Syst., (2007)