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Disambiguation of "Park, Byung Gook"

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Synchronous mirror delay for multiphase locking.

, , , , , , and . IEEE J. Solid State Circuits, 39 (1): 150-156 (2004)

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Sung Gook Park

Byung-Hoon Park

Ky Byung Park

Byung-Wook Park

Byung-Nam Park

 

Other publications of authors with the same name

Establishing Read Operation Bias Schemes for 3-D Pillar Structure Flash Memory Devices to Overcome Paired Cell Interference (PCI)., , , , , , , and . IEICE Trans. Electron., 91-C (5): 731-735 (2008)Ultrasensitive Electrical Detection of Hemagglutinin for Point-of-Care Detection of Influenza Virus Based on a CMP-NANA Probe and Top-Down Processed Silicon Nanowire Field-Effect Transistors., , , , , , , , , and 1 other author(s). Sensors, 19 (20): 4502 (2019)L-Shaped Tunneling Field-Effect Transistors for Complementary Logic Applications., , , , , , and . IEICE Trans. Electron., 96-C (5): 634-638 (2013)Synchronous mirror delay for multiphase locking., , , , , , and . IEEE J. Solid State Circuits, 39 (1): 150-156 (2004)Hardware-Based Spiking Neural Network Using a TFT-Type AND Flash Memory Array Architecture Based on Direct Feedback Alignment., , , , , , , and . IEEE Access, (2021)On-chip trainable hardware-based deep Q-networks approximating a backpropagation algorithm., , , , , , , , , and . Neural Comput. Appl., 33 (15): 9391-9402 (2021)Analyses on Current Characteristics of 3-D MOSFET Determined by Junction Doping Profiles for Nonvolatile Memory Devices., , , , , , , and . IEICE Trans. Electron., 90-C (5): 988-993 (2007)Simulation of Retention Characteristics in Double-Gate Structure Multi-Bit SONOS Flash Memory., , , , , and . IEICE Trans. Electron., 92-C (5): 659-663 (2009)Design Consideration for Vertical Nonvolatile Memory Device Regarding Gate-Induced Barrier Lowering (GIBL)., , , , , and . IEICE Trans. Electron., 92-C (5): 620-626 (2009)Zinc Tin Oxide Synaptic Device for Neuromorphic Engineering., , , , , , , , , and 4 other author(s). IEEE Access, (2020)