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Establishing Read Operation Bias Schemes for 3-D Pillar Structure Flash Memory Devices to Overcome Paired Cell Interference (PCI)., , , , , , , и . IEICE Trans. Electron., 91-C (5): 731-735 (2008)Bias Polarity Dependent Resistive Switching Behaviors in Silicon Nitride-Based Memory Cell., , , и . IEICE Trans. Electron., 99-C (5): 547-550 (2016)InGaAs/Si Heterojunction Tunneling Field-Effect Transistor on Silicon Substrate., , , , , и . IEICE Trans. Electron., 97-C (7): 677-682 (2014)Resistive Switching Characteristics of Silicon Nitride-Based RRAM Depending on Top Electrode Metals., , , , и . IEICE Trans. Electron., 98-C (5): 429-433 (2015)Characterization of 2-bit Recessed Channel Memory with Lifted-Charge Trapping Node (L-CTN) Scheme., , , , , , , , и . IEICE Trans. Electron., 91-C (5): 742-746 (2008)Simulation Study on Dependence of Channel Potential Self-Boosting on Device Scale and Doping Concentration in 2-D and 3-D NAND-Type Flash Memory Devices., , , , , и . IEICE Trans. Electron., 93-C (5): 596-601 (2010)Insertion of Ag Layer in TiN/SiNx/TiN RRAM and Its Effect on Filament Formation Modeled by Monte Carlo Simulation., , , , , , , , , и . IEEE Access, (2020)Investigation of source-to-drain capacitance by DIBL effect of silicon nanowire MOSFETs., , и . IEICE Electron. Express, 7 (19): 1499-1503 (2010)Effects of Misaligned Gate Lapping Over the Channel on Performances of Ultra-Thin Vertical-Pillar MOSFET., и . ICEIC, стр. 1-2. IEEE, (2024)Accurate Extraction of the Trap Depth from RTS Noise Data by Including Poly Depletion Effect and Surface Potential Variation in MOSFETs., , , и . IEICE Trans. Electron., 90-C (5): 968-972 (2007)