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Disambiguation of "Riesgo, Teresa"

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Hardware and Software Debugging of FPGA Based Microprocessor Systems Through Debug Logic Insertion.

, , , and . FPL, volume 3203 of Lecture Notes in Computer Science, page 1057-1061. Springer, (2004)

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To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Teresa Edenfeld

Charakterisierung der Funktion der Proteinkinase D2 als Regulator der Chromogranin-A-Sekretion in humanen BON neuroendokrinen Tumorzellen. Uni Ulm, (2010)

Teresa Schaumann

Teresa Carlomagno

Teresa Halsband

Teresa Huber

 

Other publications of authors with the same name

Customized and automated routing repair toolset towards side-channel analysis resistant dual rail logic., , , and . Microprocess. Microsystems, 38 (8): 899-910 (2014)A scalable evolvable hardware processing array., , , , and . ReConFig, page 1-7. IEEE, (2013)FPGA-Based High-Performance Embedded Systems for Adaptive Edge Computing in Cyber-Physical Systems: The ARTICo3 Framework., , , , , and . Sensors, 18 (6): 1877 (2018)Disjoint Region Partitioning for Probabilistic Switching Activity Estimation at Register Transfer Level., , and . PATMOS, volume 5349 of Lecture Notes in Computer Science, page 399-408. Springer, (2008)High-Level Power Analysis for Intellectual Property-Based Digital Systems., and . CSSP, 33 (4): 1035-1051 (2014)Evolutionary Approach to Improve Wavelet Transforms for Image Compression in Embedded Systems., , , and . EURASIP J. Adv. Signal Process., (2011)Simulation tool and case study for planning wireless sensor network., , , and . IECON, page 6024-6028. IEEE, (2012)Hardware-software integration platform for a WSN testbed based on cookies nodes., , , and . IECON, page 6013-6018. IEEE, (2012)High Level Validation of an Optimization Algorithm for the Implementation of Adaptive Wavelet Transforms in FPGAs., , , and . DSD, page 96-103. IEEE Computer Society, (2010)A Novel FPGA-based Evolvable Hardware System Based on Multiple Processing Arrays., , , , , and . IPDPS Workshops, page 182-191. IEEE, (2013)