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Optimizing simulated annealing on GPU: A case study with IC floorplanning.

, , and . ISQED, page 263-269. IEEE, (2011)

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A GPU Algorithm for IC Floorplanning: Specification, Analysis and Optimization., , , and . VLSI Design, page 159-164. IEEE Computer Society, (2011)Probabilistic Verification for Reliability of a Two-by-Two Network-on-Chip System., , , , , , and . FMICS, volume 12863 of Lecture Notes in Computer Science, page 232-248. Springer, (2021)Topologically homogeneous power-performance heterogeneous multicore systems., and . DATE, page 125-130. IEEE, (2011)DOC: Fast and accurate congestion analysis for global routing., , and . ICCD, page 508-509. IEEE Computer Society, (2012)HCI-tolerant NoC router microarchitecture., , , and . DAC, page 40:1-40:10. ACM, (2013)Power-Performance Yield optimization for MPSoCs using MILP., , and . ISQED, page 764-771. IEEE, (2012)Integrated circuit-architectural framework for PSN aware floorplanning in microprocessors., , and . ISQED, page 212-218. IEEE, (2011)Optimizing simulated annealing on GPU: A case study with IC floorplanning., , and . ISQED, page 263-269. IEEE, (2011)Stack Aware Threshold Voltage Assignment in 3-D Multicore Designs., and . IEEE Trans. Very Large Scale Integr. Syst., 20 (3): 512-522 (2012)BoostNoC: power efficient network-on-chip architecture for near threshold computing., , , and . ICCAD, page 124. ACM, (2016)