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Disambiguation of "Wong, Martin D. F."

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Hinted quad trees for VLSI geometry DRC based on efficient searching for neighbors.

, , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 15 (3): 317-324 (1996)

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Alexander D F Lahmann

Blaise F D Bourgeois

Walter Wong

Martin F Almstetter

Martin F Polaschek

 

Other publications of authors with the same name

Simultaneous Buffer-sizing and Wire-sizing for Clock Trees Based on Lagrangian Relaxation., , , and . VLSI Design, 15 (3): 587-594 (2002)Floorplan Design for Multimillion Gate FPGAs., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 25 (12): 2795-2805 (2006)On minimizing the number of L-shaped channels in building-block layout VLSI., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 12 (6): 757-769 (1993)Channel/switchbox definition for VLSI building-block layout., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 10 (12): 1485-1493 (1991)A new approach to three- or four-layer channel routing., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 7 (10): 1094-1104 (1988)A Length-Matching Routing Algorithm for High-Performance Printed Circuit Boards., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 25 (12): 2784-2794 (2006)Timing-driven routing for FPGAs based on Lagrangian relaxation., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 22 (4): 506-510 (2003)Performance-driven channel pin assignment algorithms., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 14 (7): 849-857 (1995)Placement-Proximity-Based Voltage Island Grouping Under Performance Requirement., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 26 (7): 1256-1269 (2007)Matching-based algorithm for FPGA channel segmentation design., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 20 (6): 784-791 (2001)