( en | de | ru )

 

Disambiguation of "Wong, Martin D. F."

Author of the publication

copydeleteadd this publication to your clipboard
A Length-Matching Routing Algorithm for High-Performance Printed Circuit Boards.

, and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 25 (12): 2784-2794 (2006)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Alexander D F Lahmann

Blaise F D Bourgeois

Walter Wong

Martin F Almstetter

Martin F Polaschek

 

Other publications of authors with the same name

Circuit clustering for delay minimization under area and pin constraints., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 16 (9): 976-986 (1997)Dummy-feature placement for chemical-mechanical polishinguniformity in a shallow-trench isolation process., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 21 (1): 63-71 (2002)On shifting blocks and terminals to minimize channel density., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 13 (2): 178-186 (1994)Fast Dummy-Fill Density Analysis With Coupling Constraints., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 27 (4): 633-642 (2008)Maze routing with buffer insertion and wiresizing., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 21 (10): 1205-1209 (2002)Hinted quad trees for VLSI geometry DRC based on efficient searching for neighbors., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 15 (3): 317-324 (1996)CTM-SRAF: Continuous Transmission Mask-Based Constraint-Aware Subresolution Assist Feature Generation., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 42 (10): 3402-3411 (October 2023)BSG-Route: A Length-Constrained Routing Scheme for General Planar Topology., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 28 (11): 1679-1690 (2009)Optimal net assignment., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 14 (2): 265-269 (1995)Optimal min-area min-cut replication in partitioned circuits., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 17 (11): 1175-1183 (1998)