( en | de | ru )

 

Disambiguation of "Sapatnekar, Sachin S."

Author of the publication

copydeleteadd this publication to your clipboard
Fast Analysis and Optimization of Power/Ground Networks.

, , and . ICCAD, page 477-480. IEEE Computer Society, (2000)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Sachin Arora

Sachin Deshmukh

Sachin Kinge

Sachin Kumar

Sachin Chhatwani

 

Other publications of authors with the same name

BDD decomposition for delay oriented pass transistor logic synthesis., and . IEEE Trans. Very Large Scale Integr. Syst., 13 (8): 957-970 (2005)Compact Current Source Models for Timing Analysis Under Temperature and Body Bias Variations., and . IEEE Trans. Very Large Scale Integr. Syst., 20 (11): 2104-2117 (2012)A Time-Based Intra-Memory Computing Graph Processor Featuring A* Wavefront Expansion and 2-D Gradient Control., , and . IEEE J. Solid State Circuits, 56 (7): 2281-2290 (2021)Efficient In-Memory Processing Using Spintronics., , , , , , , , and . IEEE Comput. Archit. Lett., 17 (1): 42-46 (2018)CRAM-Seq: Accelerating RNA-Seq Abundance Quantification Using Computational RAM., , , , , , , , , and . IEEE Trans. Emerg. Top. Comput., 10 (4): 2055-2071 (2022)MINFLOTRANSIT: min-cost flow based transistor sizing tool., , and . DAC, page 649-664. ACM, (2000)Designing optimized pipelined global interconnects: algorithms and methodology impact., and . ISCAS (1), page 608-611. IEEE, (2005)The impact of electromigration in copper interconnects on power grid integrity., and . DAC, page 88:1-88:6. ACM, (2013)Temperature-aware floorplanning of microarchitecture blocks with IPC-power dependence modeling and transient analysis., , and . ISLPED, page 298-303. ACM, (2006)Techniques for scalable and effective routability evaluation., , , , , , , , , and . ACM Trans. Design Autom. Electr. Syst., 19 (2): 17:1-17:37 (2014)