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Design of HV-CMOS Detectors in BCD Technology with Noise and Crosstalk Measurements.

, , , , , and . ICECS, page 398-401. IEEE, (2019)

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Characterization of an LVDS Link in 28 nm CMOS for Multi-Purpose Pattern Recognition., , , and . ISCAS, page 1-4. IEEE, (2018)Population count circuits for Associative Memories: A comparison study., , and . MOCAST, page 1-4. IEEE, (2017)The start-up circuit for a low voltage bandgap reference., and . ICECS, page 92-95. IEEE, (2014)A radiation hardened 512 kbit SRAM in 180 nm CMOS technology., , and . ICECS, page 655-658. IEEE, (2009)Design of a rad-hard library of digital cells for space applications., , and . ICECS, page 149-152. IEEE, (2008)Evaluating the impact of substrate noise on conducted EMI in automotive microcontrollers., , , , , and . EMC Compo, page 129-133. IEEE, (2013)The AM08 Associative Memory ASIC Design, Architecture and Evaluation methodology., , , , , , , , , and 9 other author(s). MOCAST, page 1-5. IEEE, (2022)Characterization of an Associative Memory Chip in 28 nm CMOS Technology., , , , , , , , , and 8 other author(s). ISCAS, page 1-5. IEEE, (2018)Properties of Digital Switching Currents in Fully CMOS Combinational Logic., , and . IEEE Trans. Very Large Scale Integr. Syst., 18 (12): 1625-1638 (2010)Synthesis of P-circuits for logic restructuring., , , , and . Integr., 45 (3): 282-293 (2012)