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Disambiguation of "Xiang, Dong"

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A Cost-Effective Scheme for Network-on-Chip Router and Interconnect Testing.

. Asian Test Symposium, page 207-212. IEEE Computer Society, (2013)

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Dong Xiang

Dong Xiang

Wei Xiang

Xuemin Xiang

Ming Xiang

 

Other publications of authors with the same name

A power-effective scan architecture using scan flip-flops clustering and post-generation filling., , and . ACM Great Lakes Symposium on VLSI, page 517-522. ACM, (2009)Scan Flip-Flop Grouping to Compress Test Data and Compact Test Responses for Launch-on-Capture Delay Testing., , and . ACM Trans. Design Autom. Electr. Syst., 17 (2): 18:1-18:24 (2012)A New Unicast-Based Multicast Scheme for Network-on-Chip Router and Interconnect Testing., and . ACM Trans. Design Autom. Electr. Syst., 21 (2): 24:1-24:23 (2016)Fitting Generalized Additive Models with the GAM Procedure. page Paper 256-26. (2001)Anàlisi de dades; GAM; Smoothing; SAS.A Pose-Normalization Method for Casting Voxel Models Using Second-Order Central Moment Matrix., , , and . IEEE Access, (2023)TM: a new and simple topology for interconnection networks., , and . J. Supercomput., 66 (1): 514-538 (2013)Constraining Transition Propagation for Low-Power Scan Testing Using a Two-Stage Scan Architecture., , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 54-II (5): 450-454 (2007)Low-Power Weighted Pseudo-Random Test Pattern Generation for Launch-on-Capture Delay Testing., , and . VTS, page 1-6. IEEE, (2020)Scan chain configuration based X-filling for low power and high quality testing., , , and . IET Comput. Digit. Tech., 4 (1): 1-13 (2010)Cooperative power scheduling for a network of MIMO links., , and . IEEE Trans. Wirel. Commun., 9 (3): 939-944 (2010)