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Disambiguation of "Lacaita, Andrea L."

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Matching requirements in LINC transmitters for OFDM signals.

, , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 53-I (7): 1572-1578 (2006)

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L Solymosi

L Bräuer

L Müller

L Eberl

L Ruess

 

Other publications of authors with the same name

Differential tuning oscillators with reduced flicker noise upconversion., , , , and . ICECS, page 33-36. IEEE, (2004)A multi-tank LC-oscillator microwave oscillator example., , , , and . ICECS, page 29-32. IEEE, (2004)A simulation and modeling environment for the analysis and design of charge redistribution DACs used in SAR ADCs., , , and . MIPRO, page 74-79. IEEE, (2014)A 2-V 2.5-GHz-104-dBc/Hz at 100 kHz fully integrated VCO with wide-band low-noise automatic amplitude control loop., , , and . IEEE J. Solid State Circuits, 36 (4): 611-619 (2001)A 72-fs-Total-Integrated-Jitter Two-Core Fractional-N Digital PLL With Digital Period Averaging Calibration on Frequency Quadrupler and True-in-Phase Combiner., , , , , , , , , and 3 other author(s). IEEE J. Solid State Circuits, 58 (3): 634-646 (March 2023)Analysis and Design of 8-to-101.6-GHz Injection-Locked Frequency Divider by Five With Concurrent Dual-Path Multi-Injection Topology., , , , and . IEEE J. Solid State Circuits, 57 (6): 1788-1799 (2022)A 12.9-to-15.1-GHz Digital PLL Based on a Bang-Bang Phase Detector With Adaptively Optimized Noise Shaping., , , , , , , , , and 4 other author(s). IEEE J. Solid State Circuits, 57 (6): 1723-1735 (2022)A 900-MS/s SAR-Based Time-Interleaved ADC With a Fully Programmable Interleaving Factor and On-Chip Scalable Background Calibrations., , , , , , , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 69 (9): 3645-3649 (2022)A varactor configuration minimizing the amplitude-to-phase noise conversion in VCOs., , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 53-I (3): 481-488 (2006)Noise Analysis and Minimization in Bang-Bang Digital PLLs., , , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 56-II (11): 835-839 (2009)