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A framework to accelerate sequential programs on homogeneous multicores., , , и . VLSI-SoC, стр. 344-347. IEEE, (2013)A model to exploit power-performance efficiency in superscalar processors via structure resizing., и . ACM Great Lakes Symposium on VLSI, стр. 215-220. ACM, (2010)POSTER: Exploiting Multi-Level Task Dependencies to Prune Redundant Work in Relax-Ordered Task-Parallel Algorithms., , , и . PACT, стр. 495-496. IEEE, (2019)In-Hardware Moving Compute to Data Model to Accelerate Thread Synchronization on Large Multicores., , , и . IEEE Micro, 40 (1): 83-92 (2020)Predictive Thermal Management for Chip Multiprocessors Using Co-designed Virtual Machines., и . HiPEAC, том 5409 из Lecture Notes in Computer Science, стр. 293-307. Springer, (2009)SSE: Security Service Engines to Accelerate Enclave Performance in Secure Multicore Processors., и . IEEE Comput. Archit. Lett., 21 (2): 129-132 (июля 2022)A self-adaptive system architecture to address transistor aging., и . DATE, стр. 81-86. IEEE, (2009)ASM: An Adaptive Secure Multicore for Co-located Mutually Distrusting Processes., , , и . ACM Trans. Archit. Code Optim., 20 (3): 32:1-32:24 (сентября 2023)Hardware Root-of-Trust implementations in Trusted Execution Environments., , , , и . IACR Cryptol. ePrint Arch., (2023)MaxK-GNN: Towards Theoretical Speed Limits for Accelerating Graph Neural Networks Training., , , , , , , , и . CoRR, (2023)