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Disambiguation of "Wong, Martin D. F."

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UI-Timer 1.0: An Ultrafast Path-Based Timing Analysis Algorithm for CPPR.

, and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 35 (11): 1862-1875 (2016)

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Alexander D F Lahmann

Blaise F D Bourgeois

Walter Wong

Martin F Almstetter

Martin F Bürgisser

 

Other publications of authors with the same name

Accelerating aerial image simulation using improved CPU/GPU collaborative computing., , , , and . Comput. Electr. Eng., (2015)Two-layer bus routing for high-speed printed circuit boards., and . ACM Trans. Design Autom. Electr. Syst., 11 (1): 213-227 (2006)An ECO routing algorithm for eliminating coupling-capacitance violations., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 25 (9): 1754-1762 (2006)A polynomial time-optimal diode insertion/routing algorithm for fixing antenna problem IC layout., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 23 (1): 141-147 (2004)On minimizing the number of L-shaped channels in building-block layout VLSI., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 12 (6): 757-769 (1993)Channel/switchbox definition for VLSI building-block layout., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 10 (12): 1485-1493 (1991)Simultaneous Escape-Routing Algorithms for Via Minimization of High-Speed Boards., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 27 (1): 84-95 (2008)Minimum replication min-cut partitioning., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 16 (10): 1221-1227 (1997)A GPU-Accelerated Framework for Path-Based Timing Analysis., , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 42 (11): 4219-4232 (November 2023)Network-flow-based multiway partitioning with area and pin constraints., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 17 (1): 50-59 (1998)