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Critical path isolation for time-to-failure extension and lower voltage operation.

Y. Masuda, M. Hashimoto, and T. Onoye. ICCAD, page 63. ACM, (2016)

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Yutaka Nojima

Yutaka Hayauchi

Yutaka Nomura

Other publications of authors with the same name

Comparing voltage adaptation performance between replica and in-situ timing monitors.Y. Masuda, J. Nagayama, H. Takeno, Y. Ogawa, Y. Momiyama, and M. Hashimoto. ICCAD, page 39. ACM, (2018)A Standard Cell Memory Based on 2T Gain Cell DRAM for Memory-Centric Accelerator Design.T. Chen, Y. Masuda, and T. Ishihara. SOCC, page 1-6. IEEE, (2023)Integration of Minimum Energy Point Tracking and Soft Real-Time Scheduling for Edge Computing.T. Komori, Y. Masuda, J. Shiomi, and T. Ishihara. ISQED, page 300-306. IEEE, (2021)Neural Network Calculations at the Speed of Light Using Optical Vector-Matrix Multiplication and Optoelectronic Activation.N. Hattori, J. Shiomi, Y. Masuda, T. Ishihara, A. Shinya, and M. Notomi. IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 104-A (11): 1477-1487 (2021)Critical Path Isolation and Bit-Width Scaling Are Highly Compatible for Voltage Over-Scalable Design.Y. Masuda, J. Nagayama, T. Cheng, T. Ishihara, Y. Momiyama, and M. Hashimoto. DATE, page 1260-1265. IEEE, (2021)Hardware-simulation correlation of timing error detection performance of software-based error detection mechanisms.Y. Masuda, M. Hashimoto, and T. Onoye. IOLTS, page 84-89. IEEE, (2016)Optoelectronic Implementation of Compact and Power-efficient Recurrent Neural Networks.T. Ichikawa, Y. Masuda, T. Ishihara, A. Shinya, and M. Notomi. ISVLSI, page 390-393. IEEE, (2022)An Optical Neural Network Architecture based on Highly Parallelized WDM-Multiplier-Accumulator.T. Ishihara, J. Shiomi, N. Hattori, Y. Masuda, A. Shinya, and M. Notomi. PHOTONICS@SC, page 15-21. IEEE, (2019)Power-aware pruning for ultrafast, energy-efficient, and accurate optical neural network design.N. Hattori, Y. Masuda, T. Ishihara, A. Shinya, and M. Notomi. DAC, page 1285-1290. ACM, (2022)MTTF-aware design methodology of error prediction based adaptively voltage-scaled circuits.Y. Masuda, and M. Hashimoto. ASP-DAC, page 159-165. IEEE, (2018)

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Disambiguation of "Masuda, Yutaka"

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Critical path isolation for time-to-failure extension and lower voltage operation.

Please choose a person to relate this publication to

Yutaka Nojima

Yutaka Hayauchi

Yutaka Nomura

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Masuda, Yutaka"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Critical path isolation for time-to-failure extension and lower voltage operation.

Please choose a person to relate this publication to

Yutaka Nojima

Yutaka Hayauchi

Yutaka Nomura

Other publications of authors with the same name

Disambiguation

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URL
DOI
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APA
Chicago
DIN 1505
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Critical path isolation for time-to-failure extension and lower voltage operation.