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Disambiguation of "Shigematsu, Satoshi"

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Hierarchical Scheduling with FPGA-based Accelerator for Flexible 5G Mobile Networks.

, , and . VTC Spring, page 1-5. IEEE, (2020)

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Satoshi Ejima

Satoshi Okawa

Satoshi Otomo

Satoshi Murayama

Satoshi Nishida

 

Other publications of authors with the same name

A pixel-level automatic calibration circuit scheme for capacitive fingerprint sensor LSIs., , , , and . IEEE J. Solid State Circuits, 37 (10): 1300-1306 (2002)A 1-V multithreshold-voltage CMOS digital signal processor for mobile phone application., , , , , and . IEEE J. Solid State Circuits, 31 (11): 1795-1802 (1996)A 1-V high-speed MTCMOS circuit scheme for power-down application circuits., , , , and . IEEE J. Solid State Circuits, 32 (6): 861-869 (1997)A novel DBA scheme for TDM-PON based mobile fronthaul., , , , , , and . OFC, page 1-3. IEEE, (2014)Fingerprint Image Enhancement by Pixel-Parallel Processing., , , , , , , and . ICPR (3), page 752-755. IEEE Computer Society, (2002)5G R&D Activities for High Capacity Technologies with Ultra High-Density Multi-Band and Multi-Access Layered Cells., , , , , , , , , and 2 other author(s). VTC Spring, page 1-5. IEEE, (2019)A 100-MHz 51.2-Gb/s packet lookup engine LSI based on missmatch detection circuit combined with linked-list hash table., , , , , and . ISPACS, page 351-356. IEEE, (2015)1-V power supply high-speed digital circuit technology with multithreshold-voltage CMOS., , , , , and . IEEE J. Solid State Circuits, 30 (8): 847-854 (August 1995)Logic and Analog Test Schemes for a Single-Chip Pixel-Parallel Fingerprint Identification LSI., , , , , , , and . IEICE Trans. Electron., 90-C (10): 1892-1899 (2007)Wire-speed verification schemes for HW/SW design of 10-Gbit/s-class large-scale NW SoC using multiple FPGAs., , , , , and . FPL, page 639-642. IEEE, (2012)