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Disambiguation of "Rylyakov, Alexander V."

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A 3.9ns 8.9mW 4×4 silicon photonic switch hybrid integrated with CMOS driver.

, , , , , , , , , , and . ISSCC, page 222-224. IEEE, (2011)

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V Saile

V Geoffroy

V Ustinov

V Adams

V Fendrich

 

Other publications of authors with the same name

40-Gb/s circuits built from a 120-GHz fT SiGe technology., , , , , , , , , and 3 other author(s). IEEE J. Solid State Circuits, 37 (9): 1106-1114 (2002)Ultra-Low-Power 10 to 285 Gb/s CMOS-Driven VCSEL-Based Optical Links Invited., , , , and . JOCN, 4 (11): B114-B123 (2012)An Adaptively Pipelined Mixed Synchronous-Asynchronous Digital FIR Filter Chip Operating at 1.3 Gigahertz., , , , and . IEEE Trans. Very Large Scale Integr. Syst., 18 (7): 1043-1056 (2010)Bang-bang digital PLLs at 11 and 20GHz with sub-200fs integrated jitter for high-speed serial communication applications., , , , , , and . ISSCC, page 94-95. IEEE, (2009)High speed circuits for short reach optical communications.. OFC, page 1-34. IEEE, (2015)Monolithically integrated silicon nanophotonics receiver in 90nm CMOS technology node., , , , , , , , , and 4 other author(s). OFC/NFOEC, page 1-3. IEEE, (2013)A 56.1Gb/s NRZ modulated 850nm VCSEL-based optical link., , , , , , , , , and 4 other author(s). OFC/NFOEC, page 1-3. IEEE, (2013)Deeply-scaled CMOS-integrated nanophotonic devices for next generation supercomputers., , , , , and . ACM Great Lakes Symposium on VLSI, page 475-476. ACM, (2011)A Wide Power-Supply Range (0.5V-to-1.3V) Wide Tuning Range (500 MHz-to-8 GHz) All-Static CMOS AD PLL in 65nm SOI., , , , and . ISSCC, page 172-173. IEEE, (2007)A 23.5 GHz PLL With an Adaptively Biased VCO in 32 nm SOI-CMOS., , , , , , , , , and 5 other author(s). IEEE Trans. Circuits Syst. I Regul. Pap., 60-I (8): 2009-2017 (2013)