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Disambiguation of "Tierno, José A."

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Bang-bang digital PLLs at 11 and 20GHz with sub-200fs integrated jitter for high-speed serial communication applications.

, , , , , , and . ISSCC, page 94-95. IEEE, (2009)

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Humberto Jorge José

Pietro Tierno

Nadine José Gonzalez

Jose A C Broekaert

José Navarrete

 

Other publications of authors with the same name

Asynchronous Parallel Prefix Computation., and . IEEE Trans. Computers, 47 (11): 1244-1252 (1998)Bang-bang digital PLLs at 11 and 20GHz with sub-200fs integrated jitter for high-speed serial communication applications., , , , , , and . ISSCC, page 94-95. IEEE, (2009)An Adaptively Pipelined Mixed Synchronous-Asynchronous Digital FIR Filter Chip Operating at 1.3 Gigahertz., , , , and . IEEE Trans. Very Large Scale Integr. Syst., 18 (7): 1043-1056 (2010)Asynchronous Circuits and Systems in Superconducting RSFQ Digital Technology., , , and . ASYNC, page 274-. IEEE Computer Society, (1998)A linearized, low-phase-noise VCO-based 25-GHz PLL with autonomic biasing., , , , , , , , , and 5 other author(s). IEEE J. Solid State Circuits, 48 (5): 1138-1150 (2013)Integrated transversal equalizers in high-speed fiber-optic systems., , , , , , and . IEEE J. Solid State Circuits, 38 (12): 2131-2137 (2003)A 1.4 pJ/bit, Power-Scalable 16×12 Gb/s Source-Synchronous I/O With DFE Receiver in 32 nm SOI CMOS Technology., , , , , , , , , and 7 other author(s). IEEE J. Solid State Circuits, 50 (8): 1917-1931 (2015)A Modular All-Digital PLL Architecture Enabling Both 1-to-2GHz and 24-to-32GHz Operation in 65nm CMOS., , , , , and . ISSCC, page 516-517. IEEE, (2008)Low-energy asynchronous memory design., and . ASYNC, page 176-185. IEEE, (1994)A 3.2GS/s 4.55b ENOB two-step subranging ADC in 45nm SOI CMOS., , , , , , , , and . CICC, page 1-4. IEEE, (2012)