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A pipeline 15-b 10-Msample/s analog-to-digital converter for ADSL applications.

, , , , , , и . ISCAS (1), стр. 396-399. IEEE, (2001)

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Gil dos Santos Guerreiro João

João Barros

João Fonseca

João Carreira

João Matos

 

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Design considerations for high resolution pipeline ADCs in digital CMOS technology., , , , , , и . ICECS, стр. 497-500. IEEE, (2001)Fully-digital Testability of a High-speed Conversion System., , и . ISCAS, стр. 1595-1598. IEEE, (1993)Termination of averaging networks in flash ADCs., и . ISCAS (1), стр. 121-124. IEEE, (2004)IC design automation from circuit level optimization to retargetable layout., , , , , , , и . ICECS, стр. 95-98. IEEE, (2001)A true logarithmic analog-to-digital pipeline converter with 1.5 bit/stage and digital correction., , и . ICECS, стр. 393-396. IEEE, (2001)A 90nm CMOS 1.2v 6b 1GS/s two-step subranging ADC., , , , , , и . ISSCC, стр. 2320-2329. IEEE, (2006)A CMOS logarithmic pipeline A/D converter with a dynamic range of 80 dB., , и . ICECS, стр. 193-196. IEEE, (2002)Analysis of the averaging technique in flash ADCs., и . ISCAS (1), стр. 849-852. IEEE, (2003)A Skill-based library for retargetable embedded analog cores., , и . DATE, стр. 768-769. IEEE Computer Society, (2001)Optimum Resolution-per-Stage in High-Speed Pipelined A/D Converters Using Self-Calibration., , и . ISCAS, стр. 525-528. IEEE, (1995)