( en | de | ru )

 

Disambiguation of "Srikanthan, Thambipillai"

Author of the publication

copydeleteadd this publication to your clipboard
High Speed Performance Estimation of Embedded Hard-core Processors in FPGA-based SoCs.

, , , and . HEART, page 2:1-2:6. ACM, (2017)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

No persons found for author name Srikanthan, Thambipillai
add a person with the name Srikanthan, Thambipillai
 

Other publications of authors with the same name

Memory-access aware work-load distribution for peak-temperature reduction of 3D multi-core embedded systems., , , and . DSP, page 1270-1273. IEEE, (2015)Custom instructions with local memory elements without expensive DMA transfers., , and . FPL, page 647-650. IEEE, (2012)Exploiting FPGA-aware merging of custom instructions for runtime reconfiguration., , and . ReCoSoC, page 1-8. IEEE, (2012)An OLE-based speech compression system for multimedia applications., , and . Microprocess. Microsystems, 22 (1): 41-48 (1998)A transputer based vehicle simulator., , , and . Microprocess. Microsystems, 19 (7): 395-404 (1995)Rapid design of area-efficient custom instructions for reconfigurable embedded processing., and . J. Syst. Archit., 55 (1): 1-14 (2009)Compiler-assisted technique for rapid performance estimation of FPGA-based processors., , and . SoCC, page 341-346. IEEE, (2011)Parallelizing the Hough Transform Computation., , and . IEEE Signal Process. Lett., (2008)Fuzzy-ART based image compression for hardware implementation., , , and . APCCAS (2), page 147-150. IEEE, (2002)Architecture-Aware Technique for Mapping Area-Time Efficient Custom Instructions onto FPGAs., , and . IEEE Trans. Computers, 60 (5): 680-692 (2011)