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Real-time scheduling on heterogeneous system-on-chip architectures using an optimised artificial neural network.

, , , and . J. Syst. Archit., 57 (4): 340-353 (2011)

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A Dynamically Reconfigurable Architecture for Low-Power Multimedia Terminals., , , and . VLSI-SOC, volume 218 of IFIP Conference Proceedings, page 51-62. Kluwer, (2001)VLSI high level synthesis of fast exact least mean square algorithms based on fast FIR filters., , , and . ICASSP, page 671-674. IEEE Computer Society, (1997)Approximate nanophotonic interconnects., , , and . NOCS, page 9:1-9:7. ACM, (2019)DART: A Dynamically Reconfigurable Architecture Dealing with Future Mobile Telecommunications Constraints., , , and . IPDPS, IEEE Computer Society, (2002)Memory aspects in signal processing and HLS tool: Some results., , , and . EUSIPCO, page 1-4. IEEE, (1996)Asynchronous timing model for high-level synthesis of DSP applications., , and . EUSIPCO, page 1-4. IEEE, (1998)Structure mémoire reconfigurable. Vers une structure de stockage faible consommation., , , and . Technique et Science Informatiques, 27 (1-2): 181-202 (2008)Teaching hardware/software system codesign using CAD tools: a case study in image synthesis., , , and . IEEE Trans. Educ., 43 (3): 277-283 (2000)Open-People: Open Power and Energy Optimization PLatform and Estimator.. PATMOS, volume 6448 of Lecture Notes in Computer Science, page 251. Springer, (2010)Mesh and Fat-Tree comparison for dynamically reconfigurable applications., , , and . ReCoSoC, volume 7551 of KIT Scientific Reports, page 157-160. KIT Scientific Publishing, (2010)