( en | de | ru )

 

Disambiguation of "Panda, Preeti Ranjan"

Author of the publication

copydeleteadd this publication to your clipboard
Exploration of Loop Unroll Factors in High Level Synthesis.

, , , , and . VLSID, page 465-466. IEEE Computer Society, (2018)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Preeti Bajaj

Satyananda Panda

Preeti Kumari

Preeti Sareen

Preeti Bhargava

 

Other publications of authors with the same name

Compressing Cache State for Postsilicon Processor Debug., , and . IEEE Trans. Computers, 60 (4): 484-497 (2011)Dynamic Thermal Management of 3D Memory through Rotating Low Power States and Partial Channel Closure., , , , , and . ACM Trans. Embed. Comput. Syst., 22 (6): 104:1-104:27 (November 2023)CoreMemDTM: Integrated Processor Core and 3D Memory Dynamic Thermal Management for Improved Performance., , and . DATE, page 1377-1382. IEEE, (2022)Array Interleaving - An Energy-Efficient Data Layout Transformation., , , , and . ACM Trans. Design Autom. Electr. Syst., 20 (3): 44:1-44:26 (2015)FastFwd: an efficient hardware acceleration technique for trace-driven network-on-chip simulation., , , and . CODES+ISSS, page 247-256. ACM, (2010)An integrated algorithm for memory allocation and assignment in high-level synthesis., , and . DAC, page 608-611. ACM, (2002)Abridged addressing: a low power memory addressing strategy.. ASP-DAC, page 892-897. IEEE, (2006)Reusing trace buffers to enhance cache performance., , and . DATE, page 572-577. IEEE, (2017)Cache aware compression for processor debug support., , and . DATE, page 208-213. IEEE, (2009)Area-Aware Cache Update Trackers for Postsilicon Validation., , and . IEEE Trans. Very Large Scale Integr. Syst., 24 (5): 1794-1807 (2016)