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Disambiguation of "Nakamura, Hiroshi"

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7.2 4Mb STT-MRAM-based cache with memory-access-aware power optimization and write-verify-write / read-modify-write scheme.

, , , , , , , , , , , , and . ISSCC, page 132-133. IEEE, (2016)

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Shin'ichiro Nakamura

Makoto Nakamura

Akira Nakamura

Hiroshi Kawabe

Hiroshi Murata

 

Other publications of authors with the same name

Logic Optimization for Asynchronous SI Controllers using Transduction Method., , , and . IWLS, page 245-250. (2002)A New 4 GHz 90 Mbps Digital Radio System Using 64-QAM Modulation., , , , and . ICC (2), page 642-645. Elsevier, (1984)Design Method of High Performance and Low Power Functional Units Considering Delay Variations., , , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 89-A (12): 3519-3528 (2006)Power Reduction Scheme of Fans in a Blade System by Considering the Imbalance of CPU Temperatures., , , , , and . GreenCom/CPSCom, page 81-87. IEEE Computer Society, (2010)Improvement of Signal Power in Intrabody Communication Using an Impedance Adjustment Circuit., , , , , and . GCCE, page 25-29. IEEE, (2022)Design and control methodology for fine grain power gating based on energy characterization and code profiling of microprocessors., , , , , , , , , and 2 other author(s). ASP-DAC, page 843-848. IEEE, (2014)New LDoS Attack in Zigbee Network and its Possible Countermeasures., , , and . SMARTCOMP, page 246-251. IEEE, (2021)GraphDEAR: An Accelerator Architecture for Exploiting Cache Locality in Graph Analytics Applications., , , , , , and . PDP, page 135-143. IEEE, (2022)A 35 ns cycle time 3.3 V only 32 Mb NAND flash EEPROM., , , , , , , , , and 2 other author(s). IEEE J. Solid State Circuits, 30 (11): 1157-1164 (November 1995)Proposal of step climbing of wheeled robot using slip ratio control., , , and . IECON, page 6545-6550. IEEE, (2013)