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Disambiguation of "Miyahara, Masaya"

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An Ultra-Low-Voltage 160 MS/s 7 Bit Interpolated Pipeline ADC Using Dynamic Amplifiers.

, , , , and . IEEE J. Solid State Circuits, 50 (6): 1399-1411 (2015)

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Other publications of authors with the same name

A 3.6 GHz fractional-N digital PLL using SAR-ADC-based TDC with-110 dBc/Hz in-band phase noise., , and . A-SSCC, page 1-4. IEEE, (2015)A 9-bit 1.8 GS/s 44 mW Pipelined ADC Using Linearized Open-Loop Amplifiers., , and . IEEE J. Solid State Circuits, 51 (10): 2210-2221 (2016)An Ultra-Low-Voltage 160 MS/s 7 Bit Interpolated Pipeline ADC Using Dynamic Amplifiers., , , , and . IEEE J. Solid State Circuits, 50 (6): 1399-1411 (2015)A 50.1-Gb/s 60-GHz CMOS Transceiver for IEEE 802.11ay With Calibration of LO Feedthrough and I/Q Imbalance., , , , , , , , , and 15 other author(s). IEEE J. Solid State Circuits, 54 (5): 1375-1390 (2019)Development of baseband processing SoC with ultrahigh-speed QAM modem and broadband radio system for demonstration experiment thereof., , , , and . ICECS, page 687-690. IEEE, (2009)A stability-improved single-opamp third-order ΣΔ modulator by using a fully-passive noise-shaping SAR ADC and passive adder., , and . ESSCIRC, page 249-252. IEEE, (2016)An All-Digital Reconfigurable Time-Domain ADC for Low-Voltage Sensor Interface in 65nm CMOS Technology., , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 98-A (2): 466-475 (2015)A 7-bit 1-GS/s Flash ADC with Background Calibration., , and . IEICE Trans. Electron., 97-C (4): 298-307 (2014)Design of Interpolated Pipeline ADC Using Low-Gain Open-Loop Amplifiers., , and . IEICE Trans. Electron., 96-C (6): 838-849 (2013)A 0.022mm2 970µW dual-loop injection-locked PLL with -243dB FOM using synthesizable all-digital PVT calibration circuits., , , , , and . ISSCC, page 248-249. IEEE, (2013)