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Clockwork: Resource-Efficient Static Scheduling for Multi-Rate Image Processing Applications on FPGAs., , and . FCCM, page 186-194. IEEE, (2021)Creating an Agile Hardware Design Flow., , , , , , , , , and 22 other author(s). DAC, page 1-6. IEEE, (2020)Using Runtime Circuit Specialization to Accelerate Simulations of Reconfigurable Architectures., and . ReConFig, page 1-6. IEEE, (2018)Type-directed scheduling of streaming accelerators., , , , , , , , and . PLDI, page 408-422. ACM, (2020)Compiling Halide Programs to Push-Memory Accelerators., , , , , , , , , and 1 other author(s). CoRR, (2021)Unified Buffer: Compiling Image Processing and Machine Learning Applications to Push-Memory Accelerators., , , , , , , and . ACM Trans. Archit. Code Optim., 20 (2): 26:1-26:26 (June 2023)AHA: An Agile Approach to the Design of Coarse-Grained Reconfigurable Accelerators and Compilers., , , , , , , , , and 23 other author(s). ACM Trans. Embed. Comput. Syst., 22 (2): 35:1-35:34 (March 2023)CoSA: Integrated Verification for Agile Hardware Design., , , , , and . FMCAD, page 1-5. IEEE, (2018)A polyhedral compiler for image processing hardware.. Stanford University, USA, (2021)