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Low-Power Divider Retiming in a 3-4 GHz Fractional-N PLL.

, , , , и . IEEE Trans. Circuits Syst. II Express Briefs, 58-II (4): 200-204 (2011)

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L Solymosi

L Bräuer

L Müller

L Eberl

L Ruess

 

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Noise Analysis and Minimization in Bang-Bang Digital PLLs., , , , , и . IEEE Trans. Circuits Syst. II Express Briefs, 56-II (11): 835-839 (2009)A varactor configuration minimizing the amplitude-to-phase noise conversion in VCOs., , , и . IEEE Trans. Circuits Syst. I Regul. Pap., 53-I (3): 481-488 (2006)A Background Calibration Technique to Control the Bandwidth of Digital PLLs., , , , , и . IEEE J. Solid State Circuits, 53 (11): 3243-3255 (2018)A 1.7 GHz Fractional-N Frequency Synthesizer Based on a Multiplying Delay-Locked Loop., , , , , и . IEEE J. Solid State Circuits, 50 (11): 2678-2691 (2015)A Wideband Fractional-N PLL With Suppressed Charge-Pump Noise and Automatic Loop Filter Calibration., , , и . IEEE J. Solid State Circuits, 48 (10): 2419-2429 (2013)Suppression of Flicker Noise Up-Conversion in a 65-nm CMOS VCO in the 3.0-to-3.6 GHz Band., , , , и . IEEE J. Solid State Circuits, 48 (10): 2375-2389 (2013)Analysis and Design of 8-to-101.6-GHz Injection-Locked Frequency Divider by Five With Concurrent Dual-Path Multi-Injection Topology., , , , и . IEEE J. Solid State Circuits, 57 (6): 1788-1799 (2022)A 12.9-to-15.1-GHz Digital PLL Based on a Bang-Bang Phase Detector With Adaptively Optimized Noise Shaping., , , , , , , , , и 4 other автор(ы). IEEE J. Solid State Circuits, 57 (6): 1723-1735 (2022)A 2-V 2.5-GHz-104-dBc/Hz at 100 kHz fully integrated VCO with wide-band low-noise automatic amplitude control loop., , , и . IEEE J. Solid State Circuits, 36 (4): 611-619 (2001)A 72-fs-Total-Integrated-Jitter Two-Core Fractional-N Digital PLL With Digital Period Averaging Calibration on Frequency Quadrupler and True-in-Phase Combiner., , , , , , , , , и 3 other автор(ы). IEEE J. Solid State Circuits, 58 (3): 634-646 (марта 2023)