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Disambiguation of "Lacaita, Andrea L."

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Low-Power Divider Retiming in a 3-4 GHz Fractional-N PLL.

, , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 58-II (4): 200-204 (2011)

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L Bräuer

L Solymosi

L Müller

L Eberl

L Ruess

 

Other publications of authors with the same name

Phase noise degradation at high oscillation amplitudes in LC-tuned VCO's., , , , and . IEEE J. Solid State Circuits, 35 (1): 96-99 (2000)A 12.5-GHz Fractional-N Type-I Sampling PLL Achieving 58-fs Integrated Jitter., , , , , , , and . IEEE J. Solid State Circuits, 57 (2): 505-517 (2022)Integrated LC oscillators for frequency synthesis in wireless applications., , and . IEEE Commun. Mag., 40 (5): 166-171 (2002)Efficient Calculation of the Impulse Sensitivity Function in Oscillators., , , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 59-II (10): 628-632 (2012)Low-Power Divider Retiming in a 3-4 GHz Fractional-N PLL., , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 58-II (4): 200-204 (2011)Matching requirements in LINC transmitters for OFDM signals., , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 53-I (7): 1572-1578 (2006)Time-to-Digital Converter for Frequency Synthesis Based on a Digital Bang-Bang DLL., , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 57-I (3): 548-555 (2010)A Wideband 3.6 GHz Digital ΔΣ Fractional-N PLL With Phase Interpolation Divider and Digital Spur Cancellation., , , and . IEEE J. Solid State Circuits, 46 (3): 627-638 (2011)A 30-GHz Digital Sub-Sampling Fractional- $N$ PLL With -238.6-dB Jitter-Power Figure of Merit in 65-nm LP CMOS., , , , , , and . IEEE J. Solid State Circuits, 54 (12): 3493-3502 (2019)Suppression of flicker noise upconversion in a 65nm CMOS VCO in the 3.0-to-3.6GHz band., , , and . ISSCC, page 50-51. IEEE, (2010)