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A 12-Gb/s DEMUX Implemented With SiGe High-Speed FPGA Circuits., , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 15 (9): 1051-1054 (2007)Boundary-Aware Multiscale Learning Perception for Remote Sensing Image Segmentation., , , , , , and . IEEE Trans. Geosci. Remote. Sens., (2023)Enabling on Demand Deployment of Middleware Services in Componentized Middleware., , , , and . CBSE, volume 6092 of Lecture Notes in Computer Science, page 113-129. Springer, (2010)A Novel Multi-Speed, Power Saving Architecture for SiGe HBT FPGA., , , , , , , and . Engineering of Reconfigurable Systems and Algorithms, page 181-187. CSREA Press, (2003)Towards Online Localization and Recovery for Faulty Components in Component-Based Applications., , , , and . COMPSAC, page 138-147. IEEE Computer Society, (2012)Hypergraph partitions., , , and . CoRR, (2019)0.18 μm CMOS integrated circuit design for impedance-based structural health monitoring., , and . IET Circuits Devices Syst., 4 (3): 227-238 (2010)Load balance and energy efficient data gathering in wireless sensor networks., , , and . Wirel. Commun. Mob. Comput., 8 (5): 645-659 (2008)The 10GHz 4: 1 MUX and 1: 4 DEMUX implemented via the gigahertz SiGe FPGA., , , , , , , , and . ACM Great Lakes Symposium on VLSI, page 141-144. ACM, (2004)A four-bit full adder implemented on fast SiGe FPGAs with novel power control scheme., , , , , , , , and . FPGA, page 248. ACM, (2003)