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Disambiguation of "Liu, Shen-Iuan"

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4-Gb/s Parallel Receivers With Adaptive Far-End Crosstalk Cancellation.

, and . IEEE Trans. Circuits Syst. II Express Briefs, 60-II (5): 252-256 (2013)

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Kai-shen Liu

Liu Liu

Liu Liu

Liu Liu

Wan Shen

 

Other publications of authors with the same name

A 40Gb/s Transimpedance-AGC Amplifier with 19dB DR in 90nm CMOS., and . ISSCC, page 54-586. IEEE, (2007)CMOS oversampling Sigma-Delta magnetic to digital converters., , , and . ISCAS (1), page 388-391. IEEE, (2001)A low-input-swing AC-DC voltage multiplier using Schottky diodes., and . A-SSCC, page 245-248. IEEE, (2014)A 0.43pJ/bit true random number generator., , and . A-SSCC, page 33-36. IEEE, (2014)A 2.4-GHz Frequency-Drift-Compensated Phase-Locked Loop With 2.43 ppm/°C Temperature Coefficient., and . IEEE Trans. Very Large Scale Integr. Syst., 27 (3): 501-510 (2019)A PVT-Tolerant MDLL Using a Frequency Calibrator and a Voltage Monitor., and . IEEE Trans. Very Large Scale Integr. Syst., 27 (11): 2698-2702 (2019)A 1 V Phase Locked Loop with Leakage Compensation in 0.13 µm CMOS Technology., and . IEICE Trans. Electron., 89-C (3): 295-299 (2006)A Fully Integrated 1.7-3.125 Gbps Clock and Data Recovery Circuit Using a Gated Frequency Detector., and . IEICE Trans. Electron., 88-C (8): 1726-1730 (2005)A 3-8 GHz Delay-Locked Loop With Cycle Jitter Calibration., and . IEEE Trans. Circuits Syst. II Express Briefs, 55-II (11): 1094-1098 (2008)A 50.8-53-GHz Clock Generator Using a Harmonic-Locked PD in 0.13- mum CMOS., , , and . IEEE Trans. Circuits Syst. II Express Briefs, 55-II (5): 404-408 (2008)