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Disambiguation of "Ichihara, Hideyuki"

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A practical approach for logic simplification based on fault acceptability for error tolerant application.

, , , and . ETS, page 1-2. IEEE, (2015)

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Hideyuki Sakamoto

 

Other publications of authors with the same name

Channel Width Test Data Compression under a Limited Number of Test Inputs and Outputs., , , and . VLSI Design, page 329-334. IEEE Computer Society, (2003)Dynamic Test Compression Using Statistical Coding., , , and . Asian Test Symposium, page 143-. IEEE Computer Society, (2001)Test Compression Based on Lossy Image Encoding., , , and . Asian Test Symposium, page 273-278. IEEE Computer Society, (2011)On Test Generation with A Limited Number of Tests., , and . Great Lakes Symposium on VLSI, page 12-15. IEEE Computer Society, (1999)An Empirical Approach to RTL Scan Path Design Focusing on Structural Interpretation in Logic Synthesis., , , and . ITC-Asia, page 55-60. IEEE, (2019)A Practical Threshold Test Generation for Error Tolerant Application., , , and . IEICE Trans. Inf. Syst., 93-D (10): 2776-2782 (2010)A Design of Reliable Linear FSMs with Equivalent States in Stochastic Computing., , and . DFT, page 1-6. IEEE, (2021)State Encoding with Stochastic Numbers for Transient Fault Tolerant Linear Finite State Machines., , , and . DFT, page 1-6. IEEE, (2019)State assignment for fault tolerant stochastic computing with linear finite state machines., , , and . ITC-Asia, page 156-161. IEEE, (2017)An Improvement of the No-Reference Test Scheme Based on False Edge Detection for Image Processing Application., , and . ITC-Asia, page 90-95. IEEE, (2022)