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An error simulation based approach to measure error coverage of formal properties.

, , , , , and . ACM Great Lakes Symposium on VLSI, page 53-58. ACM, (2002)

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Specification and Simulation of Real Time Concurrent Systems Using Standard SDL Tools., , and . SDL Forum, volume 2708 of Lecture Notes in Computer Science, page 203-217. Springer, (2003)An error simulation based approach to measure error coverage of formal properties., , , , , and . ACM Great Lakes Symposium on VLSI, page 53-58. ACM, (2002)On PSL Properties Re-use in SoC Design Flow Based on Transaction Level Modeling., , and . MTV, page 127-132. IEEE Computer Society, (2005)Concrete Impact of Formal Verification on Quality in IP Design and Implementation., , , and . ISQED, page 38-43. IEEE Computer Society, (2001)A Verification Methodology for Reconfigurable Systems., , , , , , , and . MTV, page 85-90. IEEE Computer Society, (2004)On the Use of a High-Level Fault Model to Check Properties Incompleteness., , , , and . MEMOCODE, page 145-152. IEEE Computer Society, (2003)Hybrid, Incremental Assertion-Based Verification for TLM Design Flows., , , and . IEEE Des. Test Comput., 24 (2): 140-152 (2007)Properties Incompleteness Evaluation by Functional Verification., , and . IEEE Trans. Computers, 56 (4): 528-544 (2007)Timed State Space Analysis of Real-Time Preemptive Systems., , , and . IEEE Trans. Software Eng., 30 (2): 97-111 (2004)Modeling Flexible Real Time Systems with Preemptive Time Petri Nets., , , and . ECRTS, page 279-286. IEEE Computer Society, (2003)